The present invention generally relates to so called complementary metal oxide semiconductor (CMOS) devices, and more particularly to a CMOS structure wherein a latch-up by a parasitic thyristor associated with such a structure is eliminated.
A CMOS device is a semiconductor device in which a p-channel MOS transistor and an n-channel MOS transistor are formed on a common substrate. Such a device has an advantage of low power consumption and is used widely in various integrated circuits, particularly in a large scale integrated circuit (LSI) in which a large number of semiconductor devices are assembled in a unit area of a semiconductor substrate.
In a typical CMOS device, one of the p-channel and n-channel MOS transistors is formed directly on a substrate doped to one conductive type while the other of the MOS transistors is formed in a well defined in the substrate and doped to the other conductive type.
In a typical example, a silicon substrate doped to the n-type is used and the p-channel MOS transistor is formed directly in the substrate. Further, a well doped to the p-type is defined in the substrate and the p-channel MOS transistor is formed in the well thus defined. In operation, the substrate and the well are applied with a bias voltage such that a pn-junction formed at a boundary between the substrate and the well is reversely biased. In such a structure, it is well known that a parasitic thyristor is formed between an n.sup.+ -type region formed in the p-type well as the source of the MOS transistor and a p.sup.+ -type region formed in the n-type substrate as the source of the MOS transistor. Such a parasitic thyristor tends to be turned ON responsive to a noise signal and the like particularly in a device where a large number of p-channel and n-channel MOS transistors are formed in a unit area of the substrate with a relatively short mutual separation as in the case of the LSI device. Such a phenomenon is known as "latch-up". Once the latch-up occurs, a short circuit path is formed across the p-channel and n-channel MOS transistors and the CMOS device no longer operates properly or may be damaged. This short circuit path cannot be eliminated unless the power of the CMOS device is substantially shut-off.
In order to avoid the problem of latch-up, conventional CMOS devices use a structure in which the p-channel MOS transistor and the n-channel MOS transistor are separated by a sufficient distance or a structure in which the well extends deeply into the substrate. However, such an approach increases the size of the CMOS device and is contradictory to the requirement of size reduction of the CMOS device.
Further, there is proposed the use of a heavily doped substrate on which a less doped region is grown epitaxially so that the p-channel or n-channel MOS transistors are formed in this less doped region, of an isolation trench structure for separating the p-channel and n-channel MOS transistors. Further, there is proposed an isolation structure made from a heavily doped region provided along a boundary between the well and the substrate so as to increase the junction capacitance in such a boundary area, as is disclosed in the Japanese Laid-open Patent Application No.63-244671. However, these approaches require modification of a simple basic structure of the CMOS device and cause another problem in that the process of manufacturing becomes complicated. Further, the size of the such CMOS devices cannot be reduced beyond a certain limit because of the existence of such isolation structures. Therefore, such an approach contradicts the requirement of increasing the integration density of the LSI device.